CHAPTER 138: REGISTERS VS CACHES: SPEED VS PREDICTION

The Pathfinder in question, Zephyr, was in the training room back in the pocket space.

He had rested back to full health now and was back on his feet to test out the effects of the Registers he designed.

And the effects he’d seen so far....

Zero lag time!

For the spells that could be saved in memory, there had been no lag whatsoever. Instant spell casting!

Komi was not in great shape to spar with him, but even with the tests he’d done by himself, the changes were extremely drastic.

In total, using Aegis’ definition of 8 bits = 1 byte, Zephyr now had a total of 104,166 bytes of memory in his mana node, which turned out as 101 kilobytes of memory.

This might seem very small, especially compared to modern standards where we’re used to hearing megabytes, gigabytes and terabytes...

But this was registers.

One had to know that even in modern processors, registers themselves were usually around 128 to 512 bytes, not even up to a kilobyte, and in the processors where they were more than that, it still was just a few kilobytes at most, and that was really pushing it.

The reason comes down to the nature of registers themselves.

Aegis had explained the different types of memory to Zephyr and they had still ended up going with registers alone for now simply because of its nature.

All forms of memory were graded in levels based on the speed of how they handle sending their stored information for use. The logic being that the closer they were to the main processors themselves, the faster they were.

Registers were the fastest by far. They were right in the processor itself, so the fact that there was zero lag for Zephyr when he cast his spell just now wasn’t surprising.

The next step below that were caches, which were split into three levels based on how close they were to the main processor. L1, L2, and L3 caches, with L1 being the fastest and smallest—around 32 to 64 kilobytes, L2 between 256 kilobytes to 1 megabyte, while L3 was the slowest but largest—around 4 to 384 megabytes.

They were the next fastest form of memory Zephyr could have gone for. And in fact they would have been logical, because unlike registers, with caches, steps and parts of his most frequently used spells would be saved in this memory ensuring that his mana node did not have to waste executing those parts of the spell, reducing his casting time even more...

It was basically like prediction, some level of preemptiveness was involved. He would have no control over this too, but whenever he used some specific spells very frequently, parts of them would be saved in memory so that the next time they were cast, his mana node would not have to go through the whole steps again...

Registers could not do this. There was nothing predictive or preemptive about them. They were just small, but had insane raw speed for whatever was saved.

Zephyr didn’t even consider the next level of memory at this point—Random Access Memory (RAM).

They were the slowest of the memory types by far, but because of this, they were large, usually in the gigabytes.

In a perfect scenario, Zephyr would’ve had some memory dedicated to registers just for the quickest use, instant, abrupt spells. Then he’d have his L1 cache for frequently used fragments of a spell, they’d be very small, but very fast too, L2 would be a step above that, and L3... well he couldn’t even have L3 yet because of his single mana node count. L3 caches worked best in multi-core systems, which would be equivalent to when he had more mana nodes.

For the RAM, he couldn’t even begin to think about that yet. And even if it was possible, what was the use? How much faster would it be fetching from his RAM compared to just building the spell from scratch? Were the gains going to be that noticeable?

This was where the problem lied.

Aegis in particular had analyzed that it didn’t need to take Zephyr through the standard routes of modern processing in some scenarios.

Using the RAM as an example. Aegis would very likely not even suggest it until the point where Zephyr’s mind begins to be the limiting factor. As in he has so many spells that he needs somewhere to store some so he doesn’t think about it... like a bulk storage for spells.

It was all trade offs. Fitting what Aegis knew into Zephyr’s present situation and the unique nature of mana nodes.

One had to know that regardless of all these knowledge, Zephyr still only had 5 million Transistors he could work with for memory presently, which he made into 833,333 latches, 13,020 registers, and 203 register arrays, all totalling up to a memory storage of 101 KB.

If he had decided to split some of these into even just L1 caches, and not even the other levels yet, that would reduce the number of his instant cast spells by more than half. And for what? When his casting time for most spells were sub 0.5 seconds already.

Using parts of his already little Transistor count just to shave off an extra 0.1 second off his casting time seemed like a waste. There were diminishing returns the closer below 0.5 seconds he went. So why not just use the whole thing for registers that could save a whole spell that he could basically blink into reality immediately?

The only downside to this was that whatever spell was saved in his register memory now would remain there unless ’cleared’ by him to save another spell.

It was just weighing pros and cons. And that was why Zephyr went with an all-register build this time.

Maybe when he got his second mana node, he would try building caches for some preemptive spell casting too. The more he progresses in tiers and evolves, getting more nodes, the more the caches would begin to show their needfulness. Then he could build them.

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Astrl